Conventionally, there have been semiconductor integrated circuits that have a logic reconfiguration function (hereinafter referred to as “reconfigurable logic semiconductor integrated circuits”) as typified by a field programmable gate array (FPGA).
FIG. 1 shows an overall configuration of a conventional reconfigurable logic semiconductor integrated circuit. A conventional reconfigurable logic semiconductor integrated circuit 500 shown in FIG. 1 includes a plurality of logic elements (LE) 501 arranged in a matrix. In an FPGA, which is a reconfigurable logic semiconductor integrated circuit, the logic elements 501 are composed of a look-up table (LUT). Rewriting the LUT changes relation of output to input of the logic elements 501. The logic elements 501 are interconnected by programmable wiring that is not shown. The programmable wiring programmably determines output from which logic element 501 is inputted to which logic element 501. Changing of relation of output to input of the logic elements 501 and changing of connections between the logic elements 501 provides the semiconductor integrated circuit 500 with a desired circuit function.
For the programmable wiring, connection flexibility is increased most when all the logic elements are respectively and directly interconnected. However, this requires enormous wiring resource, and thus is impractical. On the other hand, interconnecting the logic elements only on a one-to-one basis provides no flexibility. Various interconnection structures that balance wiring resource and flexibility for efficiency have been conceived. For example, a known technique using one of such structures is disclosed in Patent Reference 1.
Hereinafter, a method for mapping a desired circuit function in the reconfigurable logic semiconductor integrated circuit 500 shown in FIG. 1 is described with reference to FIG. 2. FIG. 2 shows a procedure of mapping in a conventional reconfigurable logic semiconductor integrated circuit 500. The mapping shown in FIG. 2 is executed using a synthesis tool and a place and route (P & R) tool. These tools are specialized for each of architectures of the reconfigurable logic semiconductor integrated circuits 500.
First, a user describes a circuit function to be achieved in a hardware description language such as HDL or a high-level language such as the C language (S101). Next, the synthesis tool synthesizes logic on the described circuit function (S102). Specifically, the synthesis tool divides the described circuit function into functional units each of which can be assigned to each of the logic element 501. The synthesis tool then determines connections between the divided functional units.
Subsequently, the P & R tool places the divided functional units on the logic element 501 in an actual circuit (S103). A function (relation of output to input) of each logic element 501 is thus determined.
Following this, the P & R tool routes the logic elements 501 using the programmable wiring so that the connections determined by the logic synthesis are achieved (S104).
The placing and routing above are repeated until predetermined constraints on speed (timing) and a circuit region (area) are fulfilled. The mapping ends when the constraints are fulfilled. The logic synthesis may be performed again when the predetermined constraints are not fulfilled.
Patent Reference 2 discloses a method for constructing a large-scale reconfigurable logic semiconductor integrated circuit through less design processes by interconnecting two FPGAs on a mask layout.    Patent Reference 1: Specification of U.S. Pat. No. 5,594,363    Patent Reference 2: Specification of U.S. Pat. No. 6,335,635